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1 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 MX25L4026E datasheet
2 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 contents features ................................................................................................................................................. 4 general description ........................................................................................................................ 5 pin configurations ............................................................................................................................. 5 pin description ..................................................................................................................................... 5 block diagram ...................................................................................................................................... 6 memory organization ........................................................................................................................ 7 table 1. memory organization ............................................................................................................................. 7 device operation ................................................................................................................................. 8 figure 1. serial peripheral interface modes supported ....................................................................................... 8 data protection ................................................................................................................................... 9 table 2. protected area sizes .............................................................................................................................. 9 hold feature ....................................................................................................................................... 1 0 figure 2. hold condition operation ................................................................................................................... 1 0 table 3. command definition ..................................................................................................................... 1 1 command description ...................................................................................................................... 1 2 (1) write enable (wren) ................................................................................................................................... 1 2 (2) write disable (wrdi) .................................................................................................................................... 1 2 (3) read status register (rdsr) ...................................................................................................................... 1 3 (4) write status register (wrsr) ...................................................................................................................... 1 4 table 4. protection modes .................................................................................................................................. 1 4 (5) read data bytes (read) ............................................................................................................................. 1 5 (6) read data bytes at higher speed (fast_read) ....................................................................................... 1 5 (7) dual output mode (dread) ......................................................................................................................... 1 5 (8) sector erase (se) ......................................................................................................................................... 1 5 (9) block erase (be) ........................................................................................................................................... 1 6 (10) chip erase (ce) .......................................................................................................................................... 1 6 (11) page program (pp) ..................................................................................................................................... 1 6 (12) deep power-down (dp) .............................................................................................................................. 1 7 (13) release from deep power-down (rdp), read electronic signature (res) ............................................. 1 7 (14) read identifcation (rdid) .......................................................................................................................... 1 8 (15) read electronic manufacturer id & device id (rems) .............................................................................. 1 8 table 5. id defnitions ........................................................................................................................................ 1 8 power-on state .................................................................................................................................. 1 9 electrical specifications ............................................................................................................. 2 0 absolute maximum ratings ..................................................................................................................... 2 0 figure 3.maximum negative overshoot waveform ........................................................................................... 2 0 capacitance ta = 25c, f = 1.0 mhz ............................................................................................................. 2 0 figure 4. maximum positive overshoot waveform ............................................................................................ 2 0 figure 5. input test waveforms and measurement level .............................................................. 2 1 figure 6. output loading ........................................................................................................................... 2 1
3 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 table 6. dc characteristics (temperature = -40c to 85c, vcc = 2.7v ~ 3.6v) ................................. 2 2 table 7. ac characteristics (temperature = -40c to 85 c, vcc = 2.7v ~ 3.6v) ................................. 2 3 table 8. power-up timing .................................................................................................................................. 2 4 timing analysis ....................................................................................................................................... 2 5 figure 7. serial input timing .............................................................................................................................. 2 5 figure 8. output timing ...................................................................................................................................... 2 5 figure 9. hold timing ......................................................................................................................................... 2 6 figure 10. wp# disable setup and hold timing during wrsr when srwd=1 ............................................... 2 6 figure 11. write enable (wren) sequence (command 06) ............................................................................. 2 7 figure 12. write disable (wrdi) sequence (command 04) .............................................................................. 2 7 figure 13. read status register (rdsr) sequence (command 05) ................................................................ 2 7 figure 14. write status register (wrsr) sequence (command 01) ............................................................... 2 8 figure 15. read data bytes (read) sequence (command 03) ...................................................................... 2 8 figure 16. read at higher speed (fast_read) sequence (command 0b) ................................................... 2 9 figure 17. dual output read mode sequence (command 3b) ......................................................................... 2 9 figure 18. sector erase (se) sequence (command 20) .................................................................................. 3 0 figure 19. block erase (be) sequence (command 52 or d8) .......................................................................... 3 0 figure 20. chip erase (ce) sequence (command 60 or c7) ........................................................................... 3 0 figure 21. page program (pp) sequence (command 02) ................................................................................ 3 1 figure 22. deep power-down (dp) sequence (command b9) ......................................................................... 3 1 figure 23. release from deep power-down and read electronic signature (res) sequence (command ab) .. ........................................................................................................................................................................... 3 2 figure 24. release from deep power-down (rdp) sequence (command ab) ............................................... 3 2 figure 25. read identifcation (rdid) sequence (command 9f) ...................................................................... 3 3 figure 26. read electronic manufacturer & device id (rems) sequence (command 90) .............................. 3 3 figure 27. power-up timing ............................................................................................................................... 3 4 operating conditions ...................................................................................................................... 3 5 figure 28. ac timing at device power-up ......................................................................................................... 3 5 figure 29. power-down sequence .................................................................................................................... 3 6 erase and programming performance ................................................................................... 3 7 data retention .................................................................................................................................. 3 7 latch-up characteristics ............................................................................................................. 3 7 ordering information ..................................................................................................................... 3 8 part name description .................................................................................................................... 3 9 package information ....................................................................................................................... 4 0 revision history ................................................................................................................................ 4 1
4 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 4m-bit [x 1/x 2] cmos serial flash features general ? serial peripheral interface compatible -- mode 0 and mode 3 ? 4,194,304 x 1 bit structure or 2,097,152 x 2 bits (dual output mode) structure ? 128 equal sectors with 4k byte each - any sector can be erased individually ? 8 equal blocks with 64k byte each - any block can be erased individually ? single power supply operation - 2.7 to 3.6 volt for read, erase, and program operations ? latch-up protected to 100ma from -1v to vcc +1v performance ? high performance - fast access time: 86mhz serial clock - serial clock of dual output mode: 80mhz - fast program time: 1.4ms(typ.) and 5ms(max.)/page - byte program time: 9us - fast erase time: 60ms(typ.)/sector (4k-byte per sector) ; 0.7s(typ.)/block (64k-byte per block) ? low power consumption - low active read current: 12ma(max.) at 86mhz and 4ma(max.) at 33mhz - low active programming current: 20ma (max.) - low active erase current: 20ma (max.) - low standby current: 25ua (max.) - deep power-down mode 5ua (typ.) ? minimum 100,000 erase/program cycles ? 20 years data retention software features ? input data format - 1-byte command code ? block lock protection - the bp0~bp2 status bit defnes the size of the area to be software protected against program and erase in - structions ? auto erase and auto program algorithm - automatically erases and verifes data at selected sector - automatically programs and verifes data at selected page by an internal algorithm that automatically times the program pulse widths (any page to be programed should have page in the erased state frst) ? status register feature ? electronic identifcation - jedec 2-byte device id - res command, 1-byte device id hardware features ? package - 8-pin sop (150mil) - all pb-free devices are rohs compliant
5 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 general description the device features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. the four bus signals are a clock input (sclk), a serial data input (si), a serial data output (so), and a chip select (cs#). serial access to the device is enabled by cs# input. when it is in dual output read mode, the si and so pins become sio0 and sio1 pins for data output. the device provides sequential read operation on whole chip. after program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the speci - fed page or sector/block locations will be executed. program command is executed on byte basis, or page basis, or word basis for erase command is executes on sector, or block, or whole chip basis. to provide user with ease of interface, a status register is included to indicate the status of the chip. the status read command can be issued to detect completion status of a program or erase operation via wip bit. when the device is not in operation and cs# is high, it is put in standby mode. the device utilizes macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. pin configurations symbol description cs# chip select si/sio0 serial data input (for 1 x i/o) / serial data input & output (for dual output mode) so/sio1 serial data output (for 1 x i/o) / serial data output (for dual output mode) sclk clock input wp# write protection hold# hold, to pause the device without deselecting the device vcc + 3.3v power supply gnd ground pin description 8-pin sop (150mil) 1 2 3 4 cs# so/sio1 wp# gnd vcc hold# sclk si/sio0 8 7 6 5
6 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 address generator memory array page buffer y-decoder x-decoder data register sram buffer si sclk clock generator state machine mode logic sense amplifier hv generator output buffer so cs# block diagram
7 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 table 1. memory organization memory organization block sector address range 7 127 07f000h 07ffffh : : : 112 070000h 070fffh 6 111 06f000h 06ffffh : : : 96 060000h 060fffh 5 95 05f000h 05ffffh : : : 80 050000h 050fffh 4 79 04f000h 04ffffh : : : 64 040000h 040fffh 3 63 03f000h 03ffffh : : : 48 030000h 030fffh 2 47 02f000h 02ffffh : : : 32 020000h 020fffh 1 31 01f000h 01ffffh : : : 16 010000h 010fffh 0 15 00f000h 00ffffh : : : 3 003000h 003fffh 2 002000h 002fffh 1 001000h 001fffh 0 000000h 000fffh
8 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 device operation 1. before a command is issued, status register should be checked to ensure device is ready for the intended op - eration. 2. when incorrect command is inputted to this lsi, this lsi becomes standby mode and keeps the standby mode until next cs# falling edge. in standby mode, so pin of this lsi should be high-z. 3. when correct command is inputted to this lsi, this lsi becomes active mode and keeps the active mode until next cs# rising edge. 4. input data is latched on the rising edge of serial clock(sclk) and data shifts out on the falling edge of sclk. the difference of serial peripheral interface mode 0 and mode 3 is shown as figure 1. 5. for the following instructions: rdid, rdsr, read, fast_read, dread, res and rems the shifted-in in - struction sequence is followed by a data-out sequence. after any bit of data being shifted out, the cs# can be high. for the following instructions: wren, wrdi, wrsr, se, be, ce, pp, rdp and dp the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. during the progress of write status register, program, erase operation, to access the memory array is neglect - ed and not affect the current operation of write status register, program, erase. figure 1. serial peripheral interface modes supported sclk msb cpha si 0 1 cpol 0 (serial mode 0) (serial mode 3) 1 so sclk msb shift in shift out note: cpol indicates clock polarity of serial master, cpol=1 for sclk high while idle, cpol=0 for sclk low while not transmitting. cpha indicates clock phase. the combination of cpol bit and cpha bit decides which serial mode is supported.
9 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 data protection the device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. during power up the device automatically resets the state ma - chine in the standby mode. in addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specifc command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from vcc power-up and power-down transition or system noise. ? valid command length checking: the command length will be checked whether it is at byte base and completed on byte boundary. ? write enable (wren) command: wren command is required to set the write enable latch bit (wel) before other command to change data. the wel bit will return to reset stage under following situation: - power-up - write disable (wrdi) command completion - write status register (wrsr) command completion - page program (pp) command completion - sector erase (se) command completion - block erase (be) command completion - chip erase (ce) command completion ? deep power down mode: by entering deep power down mode, the fash device also is under protected from writing all commands except release from deep power down mode command (rdp) and read electronic sig - nature command (res). ? software protection mode (spm): by using bp0-bp2 bits to set the part of flash protected from data change. ? hardware protection mode (hpm): by using wp# going low to prote ct the bp0-bp2 bits and srwd bit from data change. table 2. protected area sizes status bit protect level 4m bp2 bp1 bp0 0 0 0 0 (none) none 0 0 1 1 (1 block) block 7 0 1 0 2 (2 blocks) block 6-7 0 1 1 3 (4 blocks) block 4-7 1 0 0 4 (8 blocks) all 1 0 1 5 (all) all 1 1 0 6 (all) all 1 1 1 7 (all) all
10 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 hold feature hold# pin signal goes low to hold any serial communications with the device. the hold feature will not stop the operation of write status register, programming, or erasing in progress. the operation of hold requires chip select (cs#) keeping low and starts on falling edge of hold# pin signal while serial clock (sclk) signal is being low (if serial clock signal is not being low, hold operation will not start until serial clock signal being low). the hold condition ends on the rising edge of hold# pin signal while se - rial clock(sclk) signal is being low( if serial clock signal is not being low, hold operation will not end until serial clock being low), see figure 2. hold# sclk hold condition (standard use) hold condition (non-standard use) the serial data output (so) is high impedance, both serial data input (si) and serial clock (sclk) are don't care during the hold operation. if chip select (cs#) drives high during hold operation, it will reset the internal logic of the device. to re-start communication with chip, the hold# must be at high and cs# must be at low. figure 2. hold condition operation
11 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 table 3. command definition command (byte) wren (write enable) wrdi (write disable) wrsr (write status register) rdid (read identi- fcation) rdsr (read status register) read (read data) fast read (fast read data) 1st 06 hex 04 hex 01 hex 9f hex 05 hex 03 hex 0b hex 2nd ad1 ad1 3rd ad2 ad2 4th ad3 ad3 5th x action sets the (wel) write enable latch bit reset the (wel) write enable latch bit to write new status register output the manufacturer id and 2-byte device id to read out the status register n bytes read out until cs# goes high n bytes read out until cs# goes high command (byte) dp (deep power down) rdp (release from deep power-down) 1st b9 hex ab hex 2nd 3rd 4th 5th action enters deep power down mode release from deep power down mode (1) add=00h will output the manufacturer's id frst and add=01h will output device id frst. (2) it is not recommended to adopt any other code which is not in the above command defnition table. command (byte) res (read electronic id) rems (read electronic manufacturer & device id) dread (double output mode command) se (sector erase) be (block erase) ce (chip erase) pp (page program) 1st ab hex 90 hex 3b hex 20 hex 52 or d8 hex 60 or c7 hex 02 hex 2nd x x ad1 ad1 ad1 ad1 3rd x x ad2 ad2 ad2 ad2 4th x add(1) ad3 ad3 ad3 ad3 5th dummy action to read out 1-byte device id output the manufacturer id and device id n bytes read out by dual output until cs# goes high to erase the selected sector to erase the selected block to erase whole chip to program the selected page
12 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 command description (1) write enable (wren) the write enable (wren) instruction is for setting write enable latch (wel) bit. for those instructions like pp, se, be, ce, and wrsr, which are intended to change the device content, should be set every time after the wren in - struction setting the wel bit. the sequence is shown as figure 1 1 . (2) write disable (wrdi) the write disable (wrdi) instruction is for resetting write enable latch (wel) bit. the sequence is shown as figure 1 2 . the wel bit is reset by following situations: - power-up - write disable (wrdi) instruction completion - write status register (wrsr) instruction completion - page program (pp) instruction completion - sector erase (se) instruction completion - block erase (be) instruction completion - chip erase (ce) instruction completion
13 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 (3) read status register (rdsr) the rdsr instruction is for reading status register bits. the read status register can be read at any time (even in program/erase/write status register condition) and continuously. it is recommended to check the write in progress (wip) bit before sending a new instruction when a program, erase, or write status register operation is in progress. the sequence is shown as figure 1 3 . the defnition of the status register bits is as below: wip bit. the write in progress (wip) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. when wip bit sets to 1, which means the device is busy in program/erase/write status register progress. when wip bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. wel bit. the write enable latch (wel) bit, a volatile bit, indicates whether the device is set to internal write enable latch. when wel bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. when wel bit sets to 0, which means no internal write enable latch; the de - vice will not accept program/erase/write status register instruction. bp2, bp1, bp0 bits. the block protect (bp2, bp1, bp0) bits, volatile bits, indicate the protected area(as defned in table 2) of the device to against the program/erase instruction without hardware protection mode being set. to write the block protect (bp2, bp1, bp0) bits requires the write status register (wrsr) instruction to be executed. those bits defne the protected area of the memory to against page program (pp), sector erase (se), block erase (be) and chip erase (ce) instructions (only if all block protect bits set to 0, the ce instruction can be executed) srwd bit. the status register write disable (srwd) bit, volatile bit, is operated together with write protection (wp#) pin for providing hardware protection mode. the hardware protection mode requires srwd sets to 1 and wp# pin signal is low stage. in the hardware protection mode, the write status register (wrsr) instruction is no longer ac - cepted for execution and the srwd bit and block protect bits (bp2, bp1, bp0) are read only. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 srwd status register write protect 0 0 bp2 (the level of protected block) bp1 (the level of protected block) bp0 (the level of protected block) wel (write enable latch) wip (write in progress bit) 1= status register write disable (note 2) 0 0 (note 1) (note 1) (note 1) 1=write enable 0=not write enable 1=write operation 0=not in write operation note: 1. see the table "protected area sizes". the bp0 ~ bp2 default value are "1" (protected). 2. the srwd default value is "0".
14 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 (4) write status register (wrsr) the wrsr instruction is for changing the values of status register bits. before sending wrsr instruction, the write enable (wren) instruction must be decoded and executed to set the write enable latch (wel) bit in ad - vance. the wrsr instruction can change the value of block protect (bp2, bp1, bp0) bits to defne the protected area of memory (as shown in table 2). the wrsr also can set or reset the status register write disable (srwd) bit in accordance with write protection (wp#) pin signal. the wrsr instruction cannot be executed once the hard - ware protected mode (hpm) is entered. the sequence is shown as figure 1 4 . the wrsr instruction has no effect on b6, b5, b4, b1, b0 of the status register. the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. the self-timed write status register cycle time (tw) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the write status register cycle is in progress. the wip sets 1 during the tw timing, and sets 0 when write status register cycle is completed, and the write enable latch (wel) bit is reset. table 4. protection modes note: 1. as defned by the values in the block protect (bp2, bp1, bp0) bits of the status register, as shown in table 2 . as the above table showing, the summary of the software protected mode (spm) and hardware protected mode (hpm). software protected mode (spm): - when srwd bit=0, no matter wp# is low or high, the wren instruction may set the wel bit and can change the values of srwd, bp2, bp1, bp0. the protected area, which is defned by bp2, bp1, bp0, is at software protected mode (spm). - when srwd bit=1 and wp# is high, the wren instruction may set the wel bit can change the values of srwd, bp2, bp1, bp0. the protected area, which is defned by bp2, bp1, bp0, is at software protected mode (spm). note: if srwd bit=1 but wp# is low, it is impossible to write the status register even if the wel bit has previously been set. it is rejected to write the status register and not be executed. hardware protected mode (hpm): - when srwd bit=1, and then wp# is low (or wp# is low before srwd bit=1), it enters the hardware protected mode (hpm). the data of the protected area is protected by software protected mode by bp2, bp1, bp0 and hardware protected mode by the wp# to against data modifcation. note: to exit the hardware protected mode requires wp# driving high once the hardware protected mode is entered. if the wp# pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via bp2, bp1, bp0. mode status register condition wp# and srwd bit status memory software protection mode (spm) status register can be written in (wel bit is set to "1") and the srwd, bp2-bp0 bits can be changed wp#=1 and srwd bit=0, or wp#=0 and srwd bit=0, or wp#=1 and srwd=1 the protected area cannot be program or erase. hardware protection mode (hpm) the srwd, bp2-bp0 of status register bits cannot be changed wp#=0, srwd bit=1 the protected area cannot be program or erase.
15 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 (5) read data bytes (read) the read instruction is for reading data out. the address is latched on rising edge of sclk, and data shifts out on the falling edge of sclk at a maximum frequency fr. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence is shown as figure 1 5 . (6) read data bytes at higher speed (fast_read) the fast_read instruction is for quickly reading data out. the address is latched on rising edge of sclk, and data of each bit shifts out on the falling edge of sclk at a maximum frequency fc. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single fast_read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence is shown as figure 1 6 . while program/erase/write status register cycle is in progress, fast_read instruction is rejected without any im - pact on the program/erase/write status register current cycle. (7) dual output mode (dread) the dread instruction enable double throughput of serial flash in read mode. the address is latched on rising edge of sclk, and data of every two bits(interleave on 1i/2o pins) shift out on the falling edge of sclk at a maxi - mum frequency ft. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single dread instruc - tion. the address counter rolls over to 0 when the highest address has been reached. once writing dread instruc - tion, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. the sequence is shown as figure 1 7 . while program/erase/write status register cycle is in progress, dread instruction is rejected without any impact on the program/erase/write status register current cycle. the dread only perform read operation. program/erase /read id/read status....operation do not support dread throughputs. (8) sector erase (se) the sector erase (se) instruction is for erasing the data of the chosen sector to be "1". a write enable (wren) in - struction must execute to set the write enable latch (wel) bit before sending the sector erase (se). any address of the sector (see table 1) is a valid address for sector erase (se) instruction. the cs# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. address bits [am-a12] (am is the most signifcant address) select the sector address.
16 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 the sequence is shown as figure 1 8 . the self-timed sector erase cycle time (tse) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the sector erase cycle is in progress. the wip sets 1 during the tse timing, and sets 0 when sector erase cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp2, bp1, bp0 bits, the sector erase (se) instruction will not be executed on the page. (9) block erase (be) the block erase (be) instruction is for erasing the data of the chosen block to be "1". a write enable (wren) in - struction must execute to set the write enable latch (wel) bit before sending the block erase (be). any address of the block (see table 1) is a valid address for block erase (be) instruction. the cs# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. the sequence is shown as figure 19 . the self-timed block erase cycle time (tbe) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the sector erase cycle is in progress. the wip sets 1 during the tbe timing, and sets 0 when sector erase cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp2, bp1, bp0 bits, the block erase (be) instruction will not be executed on the page. (10) chip erase (ce) the chip erase (ce) instruction is for erasing the data of the whole chip to be "1". a write enable (wren) instruc - tion must execute to set the write enable latch (wel) bit before sending the chip erase (ce). any address of the sector (see table 1) is a valid address for chip erase (ce) instruction. the cs# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not ex - ecuted. the sequence is shown as figure 2 0 . the self-timed chip erase cycle time (tce) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the chip erase cycle is in progress. the wip sets 1 during the tce timing, and sets 0 when chip erase cycle is completed, and the write enable latch (wel) bit is reset. if the chip is protected by bp2, bp1, bp0 bits, the chip erase (ce) instruction will not be executed. it will be only executed when bp2, bp1, bp0 all set to "0". (11) page program (pp) the page program (pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the page program (pp). the device pro - grams only the last 256 data bytes sent to the device. if the entire 256 data bytes are going to be programmed, a7- a0 (the eight least signifcant address bits) should be set to 0. if the eight least signifcant address bits (a7-a0) are not all 0, all transmitted data going beyond the end of the current page are programmed from the start address of the same page (from the address a7-a0 are all 0). if more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be disregarded. if less than 256 bytes are sent to the device, the data is programmed at the requested address of the page without effect on other address of the same page.
17 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 (12) deep power-down (dp) the deep power-down (dp) instruction is for setting the device on the minimizing the power consumption (to enter - ing the deep power-down mode), the standby current is reduced from isb1 to isb2). the deep power-down mode requires the deep power-down (dp) instruction to enter, during the deep power-down mode, the device is not ac - tive and all write/program/erase instruction are ignored. when cs# goes high, it's only in standby mode not deep power-down mode. it's different from standby mode. the sequence is shown as figure 2 2 . once the dp instruction is set, all instruction will be ignored except the release from deep power-down mode (rdp) and read electronic signature (res) instruction. (res instruction to allow the id been read out). when power- down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. for rdp instruction the cs# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. as soon as chip select (cs#) goes high, a delay of tdp is required before entering the deep power-down mode and reducing the current to isb2. (13) release from deep power-down (rdp), read electronic signature (res) the release from deep power-down (rdp) instruction is terminated by driving chip select (cs#) high. when chip select (cs#) is driven high, the device is put in the stand-by power mode. if the device was not previously in the deep power-down mode, the transition to the stand-by power mode is immediate. if the device was previously in the deep power-down mode, though, the transition to the stand-by power mode is delayed by tres2, and chip select (cs#) must remain high for at least tres2(max), as specifed in table 7 . once in the stand-by power mode, the device waits to be selected, so that it can receive, decode and execute instructions. res instruction is for reading out the old style of 8-bit electronic signature, whose values are shown as table of id defnitions. this is not the same as rdid instruction. it is not recommended to use for new design. for new deisng, please use rdid instruction. even in deep power-down mode, the rdp and res are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/ write cycle in progress. the sequence is shown as figure 2 3 and figure 2 4 . the res instruction is ended by cs# goes high after the id been read out at least once. the id outputs repeat - edly if continuously send the additional clock cycles on sclk while cs# is at low. if the device was not previously in deep power-down mode, the device transition to standby mode is immediate. if the device was previously in deep power-down mode, there's a delay of tres2 to transit to standby mode, and cs# must remain to high at least tres2(max). once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute the sequence is shown as figure 21 . the cs# must be kept to low during the whole page program cycle; the cs# must go high exactly at the byte boundary( the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be ex - ecuted. the self-timed page program cycle time (tpp) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the page program cycle is in progress. the wip sets 1 during the tpp timing, and sets 0 when page program cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp2, bp1, bp0 bits, the page program (pp) instruction will not be executed.
18 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 instruction. the rdp instruction is for releasing from deep power down mode. (14) read identifcation (rdid) the rdid instruction is for reading the manufacturer id of 1-byte and followed by device id of 2-byte. the mxic manufacturer id is c2(hex), the memory type id is 20(hex) as the frst-byte device id, and the individual device id of second-byte id is as followings: 13(hex) for MX25L4026E. the sequence is shown as figure 25 while program/erase operation is in progress, it will not decode the rdid instruction, so there's no effect on the cy - cle of program/erase operation which is currently in progress. when cs# goes high, the device is at standby stage. (15) read electronic manufacturer id & device id (rems) the rems instruction is an alternative to the release from power-down/device id instruction that provides both the jedec assigned manufacturer id and the specifc device id. the rems instruction is very similar to the release from power-down/device id instruction. the instruction is initi - ated by driving the cs# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes address (a7~a0). after which, the manufacturer id for mxic (c2h) and the device id are shifted out on the falling edge of sclk with most signifcant bit (msb) frst as shown in figure 2 6 . the device id values are listed in table 5. id defnitions. if the one-byte address is initially set to 01h, then the device id will be read frst and then followed by the manufacturer id. the manufacturer and device ids can be read continuously, alternating from one to the other. the instruction is completed by driving cs# high. table 5. id defnitions command type MX25L4026E rdid command manufacturer id memory type memory density c2 20 13 res command electronic id 12 rems command manufacturer id device id c2 12
19 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 power-on state the device is at below states when power-up: - standby mode ( please note it is not deep power-down mode) - write enable latch (wel) bit is reset the device must not be selected during power-up and power-down stage unless the vcc achieves below correct level: - vcc minimum at power-up stage and then after a delay of tvsl - gnd at power-down please note that a pull-up resistor on cs# may ensure a safe and proper power-up/down level. an internal power-on reset (por) circuit may protect the device from data corruption and inadvertent data change during power up state. for further protection on the device, if the vcc does not reach the vcc minimum level, the correct operation is not guaranteed. the write, read, erase, and program command should be sent after the below time delay: - tvsl after vcc reached vcc minimum level the device can accept read command after vcc reached vcc minimum and a time delay of tvsl. please refer to the fgure of "power-up timing". note: - to stabilize the vcc level, the vcc rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uf)
20 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and functional operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. 2. specifcations contained within the following tables are subject to change. 3. during voltage transitions, all pins may overshoot to 4.6v or -0.5v for period up to 20ns. 4. all input and output pins may overshoot to vcc+0.5v while vcc+0.5v is smaller than or equal to 4.6v. absolute maximum ratings electrical specifications capacitance ta = 25 c, f = 1.0 mhz symbol parameter min. typ max. unit conditions cin input capacitance 6 pf vin = 0v cout output capacitance 8 pf vout = 0v figure 3.maximum negative overshoot waveform 0v -0.5v 20ns figure 4. maximum positive overshoot waveform 4.6v 3.6v 20ns rating value ambient operating temperature industrial (i) grade -40c to 85c storage temperature -55c to 125c applied input voltage -0.5v to 4.6v applied output voltage -0.5v to 4.6v vcc to ground potential -0.5v to 4.6v
21 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 device under test diodes=in3064 or equivalent cl 6.2k ohm 2.7k ohm +3.3v cl=30pf including jig capacitance figure 5. input test waveforms and measurement level ac measurement level input timing referance level output timing referance level 0.8vcc 0.7vcc 0.3vcc 0.5vcc 0.2vcc note: input pulse rise and fall time are <5ns figure 6. output loading
22 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 symbol parameter notes min. typ. max. units test conditions ili input load current 1 2 ua vcc = vcc max vin = vcc or gnd ilo output leakage current 1 2 ua vcc = vcc max vin = vcc or gnd isb1 vcc standby current 1 25 ua vin = vcc or gnd cs# = vcc isb2 deep power-down current 5 10 ua vin = vcc or gnd cs# = vcc icc1 vcc read 1 12 ma f=86mhz sclk=0.1vcc/0.9vcc, so=open 12 ma f=66mhz sclk=0.1vcc/0.9vcc, so=open 4 ma f=33mhz sclk=0.1vcc/0.9vcc, so=open icc2 vcc program current (pp) 1 20 ma program in progress cs# = vcc icc3 vcc write status register (wrsr) current 15 ma program status register in progress, cs#=vcc icc4 vcc sector erase current (se) 1 15 ma erase in progress, cs#=vcc icc5 vcc chip erase current (ce) 1 20 ma erase in progress, cs#=vcc vil input low voltage -0.5 0.3vcc v vih input high voltage 0.7vcc vcc+0.4 v vol output low voltage 0.4 v iol = 1.6ma voh output high voltage vcc-0.2 v ioh = -100ua vwi low vcc write inhibit voltage 3 2.1 2.3 2.5 v table 6. dc characteristics (temperature = -40 c to 85 c, vcc = 2.7v ~ 3.6v) notes: 1. typical values at vcc = 3.3v, t = 25c. these currents are valid for all product versions (package and speeds). 2. typical value is calculated by simulation. 3. not 100% tested.
23 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 table 7. ac characteristics (temperature = -40 c to 85 c, vcc = 2.7v ~ 3.6v) symbol alt. parameter min. typ. max. unit fsclk fc clock frequency for the following instructions: fast_read, pp, se, be, ce, dp, res,rdp wren, wrdi, rdid, rdsr, wrsr dc 86 mhz frsclk fr clock frequency for read instructions dc 33 mhz ftsclk ft clock frequency for dread instructions dc 80 mhz tch(1) tclh clock high time @33mhz 13 ns @86mhz 5.5 ns tcl(1) tcll clock low time @33mhz 13 ns @86mhz 5.5 ns tclch(2) clock rise time (3) (peak to peak) 0.1 v/ns tchcl(2) clock fall time (3) (peak to peak) 0.1 v/ns tslch tcss cs# active setup time (relative to sclk) 7 ns tchsl cs# not active hold time (relative to sclk) 7 ns tdvch tdsu data in setup time 2 ns tchdx tdh data in hold time 5 ns tchsh cs# active hold time (relative to sclk) 7 ns tshch cs# not active setup time (relative to sclk) 7 ns tshsl tcsh cs# deselect time read 15 ns write 40 ns tshqz(2) tdis output disable time 6 ns tclqv tv clock low to output valid 30pf 8 ns 15pf 6 ns tclqx tho output hold time 0 ns thlch hold# setup time (relative to sclk) 5 ns tchhh hold# hold time (relative to sclk) 5 ns thhch hold setup time (relative to sclk) 5 ns tchhl hold hold time (relative to sclk) 5 ns thhqx(2) tlz hold to output low-z 6 ns thlqz(2) thz hold# to output high-z 6 ns twhsl(4) write protect setup time 20 ns tshwl(4) write protect hold time 100 ns tdp(2) cs# high to deep power-down mode 10 us tres1(2) cs# high to standby mode without electronic signature read 8.8 us tres2(2) cs# high to standby mode with electronic signature read 8.8 us tw(6) write status register cycle time 5 15 ms tbp byte-program 9 300 us tpp page program cycle time 1.4 5 ms tse sector erase cycle time 60 ms tbe block erase cycle time 0.7 2 s tce chip erase cycle time 3.7 7.5 s note: 1. tch + tcl must be greater than or equal to 1/f (fc or fr). 2. value guaranteed by characterization, not 100% tested in production. 3. expressed as a slew-rate. 4. only applicable as a constraint for a wrsr instruction when srwd is set at 1. 5. test condition is shown as figure 3 .
24 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 symbol parameter min. max. unit tvsl(1) vcc(min) to cs# low 10 us initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). note: 1. the parameter is characterized only. table 8. power-up timing
25 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 figure 7. serial input timing sclk si cs# msb so tdvch high-z lsb tslch tchdx tchcl tclch tshch tshsl tchsh tchsl figure 8. output timing lsb addr.lsb in tshqz tch tcl tclqx tclqv tclqv sclk so cs# si timing analysis
26 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 figure 9. hold timing tchhl thlch tclhs thhch tchhh thhqx thlqz tclhh sclk so cs# hold# * si is "don't care" during hold operation. figure 10. wp# disable setup and hold timing during wrsr when srwd=1 high-z 01 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 twhsl tshwl sclk si cs# wp# so
27 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 figure 11. write enable (wren) sequence (command 06) 2 1 34567 high-z 0 06 command sclk si cs# so figure 12. write disable (wrdi) sequence (command 04) 2 1 34567 high-z 0 04 command sclk si cs# so 2 1 3456789 10 11 12 13 14 15 command 0 7 6543210 status register out high-z msb 7 6543210 status register out msb 7 sclk si cs# so 05 figure 13. read status register (rdsr) sequence (command 05)
28 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 figure 14. write status register (wrsr) sequence (command 01) 2 1 345678 9 10 11 12 13 14 15 status register in 0 76543 2 0 1 msb sclk si cs# so 01 high-z command sclk si cs# so 23 2 1 3456789 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 76543 1 7 0 data out 1 24-bit address 0 msb msb 2 39 data out 2 03 high-z command figure 15. read data bytes (read) sequence (command 03)
29 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 23 2 1 3456789 10 28 29 30 31 22 21 3210 high-z 24 bit address 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 765432 0 1 data out 1 dummy byte msb 7 6543210 data out 2 msb msb 7 47 765432 0 1 35 sclk si cs# so sclk si cs# so 0b command figure 16. read at higher speed (fast_read) sequence (command 0b) figure 17. dual output read mode sequence (command 3b) high impedance 2 1 345678 0 sclk si/so0 so/so1 cs# 9 10 11 30 31 32 3b(hex) dummy address bit23, bit22, bit21...bit0 data bit6, bit4, bit2...bit0, bit6, bit4.... data bit7, bit5, bit3...bit1, bit7, bit5.... 39 40 41 42 43 8 bit instruction 24 bit address 8 dummy cycle data output
30 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 figure 18. sector erase (se) sequence (command 20) 24 bit address 2 1 3456789 29 30 31 0 23 22 2 1 0 msb sclk cs# si 20 command note: se command is 20(hex). figure 19. block erase (be) sequence (command 52 or d8) 24 bit address 2 1 3456789 29 30 31 0 23 22 2 0 1 msb sclk cs# si 52 or d8 command note: be command is 52 or d8(hex). figure 20. chip erase (ce) sequence (command 60 or c7) 2 1 34567 0 60 or c7 sclk si cs# command note: ce command is 60(hex) or c7(hex).
31 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 42 41 43 44 45 46 47 48 49 50 52 53 54 55 40 23 2 1 3456789 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 24-bit address 0 765432 0 1 data byte 1 39 51 765432 0 1 data byte 2 765432 0 1 data byte 3 data byte 256 2079 2078 2077 2076 2075 2074 2073 765432 0 1 2072 msb msb msb msb msb sclk cs# si sclk cs# si 02 command figure 21. page program (pp) sequence (command 02) figure 22. deep power-down (dp) sequence (command b9) 2 1 34567 0 t dp deep power-down mode stand-by mode sclk cs# si b9 command
32 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 figure 23. release from deep power-down and read electronic signature (res) sequence (command ab) 23 2 1 3456789 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 765432 0 1 high-z electronic signature out 3 dummy bytes 0 msb stand-by mode deep power-down mode msb t res2 sclk cs# si so ab command figure 24. release from deep power-down (rdp) sequence (command ab) 2 1 34567 0 t res1 stand-by mode deep power-down mode high-z sclk cs# si so ab command
33 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 2 1 3456789 10 11 12 13 14 15 command 0 manufacturer identification high-z msb 15 14 13 3210 device identification msb 7 6 5 3 2 1 0 16 17 18 28 29 30 31 sclk si cs# so 9f figure 26. read electronic manufacturer & device id (rems) sequence (command 90) 15 14 13 3 2 1 0 2 1 3456789 10 2 dummy bytes 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 765432 0 1 manufacturer id add (1) msb 7 6543210 device id msb msb 7 47 765432 0 1 35 31 30 29 28 sclk si cs# so sclk si cs# so x 90 high-z command notes: (1) add=00h will output the manufacturer's id frst and add=01h will output device id frst. figure 25. read identifcation (rdid) sequence (command 9f)
34 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 figure 27. power-up timing v cc v cc (min) chip selection is not allowed tvsl time device is fully accessible v cc (max)
35 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 notes : 1. sampled, not 100% tested. 2. for ac spec tchsl, tslch, tdvch, tchdx, tshsl, tchsh, tshch, tchcl, tclch in the fgure, please refer to "ac characteristics" table. symbol parameter notes min. max. unit tvr vcc rise time 1 0.5 500000 us/v operating conditions at device power-up and power-down ac timing illustrated in figure 28 and figure 29 are the supply voltages and the control signals at device power-up and power-down. if the timing in the fgures is ignored, the device will not operate correctly . during power-up and power down, cs# needs to follow the voltage applied on vcc to keep the device not be se - lected. the cs# can be driven low when vcc reach vcc(min.) and wait a period of tvsl. sclk si cs# vcc msb in so tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl tvr vcc(min) gnd figure 28. ac timing at device power-up
36 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 figure 29. power-down sequence during power down, cs# needs to follow the voltage drop on vcc to avoid mis-operation. c s # sclk v c c
37 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 erase and programming performance parameter min. typ. (1) max. (2) unit write status register cycle time (4) 5 15 ms sector erase time 60 ms block erase time 0.7 2 s chip erase time 3.7 7.5 s byte program time (via page program command) 9 300 us page program time 1.4 5 ms erase/program cycle 100,000 cycles note: 1. typical program and erase time assumes the following conditions: 25c, 3.3v, and checker board pattern. 2. under worst conditions of 85c and 2.7v. 3. system-level overhead is the time required to execute the frst-bus-cycle sequence for the programming com - mand. min. max. input voltage with respect to gnd on all power pins, si, cs# -1.0v 2 vccmax input voltage with respect to gnd on so -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 3.0v, one pin at a time. latch-up characteristics data retention parameter condition min. max. unit data retention 55?c 20 years
38 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 ordering information part no. clock (mhz) operating current(ma) standby current(ua) temperature package remark MX25L4026Em1i-12g 86 12 10 -40~85c 8-sop (150mil) pb-free
39 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 part name description mx 25 l 12 m1 i g option: g: pb-free speed: 12: 86mhz temperature range: i: industrial (-40c to 85c) package: m1: 150mil 8-sop density & mode: 4026e: 4mb type: l: 3v device: 25: serial flash 4026e
40 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 package information
41 p/n: pm1583 MX25L4026E rev. 1.0, jul. 02, 2010 revision history revision no. description page date 0.01 1. modifed "erase and programming performance" p40 apr/14/2010 2. revised "parameter id (2)" p21 0.02 1. modifed " initial delivery state" description p27 may/21/2010 2. modifed otp capable data from 1 to 0 p21 3. changed wording from dmc to sfdp p4,8,11,19 4. changed title from "advanced information" to "preliminary" p4 5. corrected max. write status register cycle time p40 6. revised sfdp sequence description p19 1.0 1. removed preliminary p4 jul/02/2010 2. removed sfdp sequence description & content table p4,8,11,19 3. modifed write status register cycle time p23,37 4. removed write status register cycle time in notes p23,37
MX25L4026E 42 macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure of a single component could cause death, personal injury, severe physical damage, or other substan - tial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft and military application. macronix and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due to use of macronix's products in the prohibited applications. copyright? macronix international co., ltd. 2010. all rights reserved. macronix, mxic, mxic logo, mx logo, are trademarks or registered trademarks of macronix international co., ltd. the names and brands of other companies are for identifcation purposes only and may be claimed as the property of the respective companies. for the contact and order information, please visit macronixs web site at: http://www.macronix.com macronix international co., ltd. reserves the right to change product and specifcations without notice.

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